Principal Engineer, Physical Design Engineering

hace 4 semanas

Valencia, Valencia, España Analog Devices A tiempo completo
About Analog Devices

Analog Devices, Inc. is a global leader in the semiconductor industry, bridging the physical and digital worlds to enable breakthroughs at the Intelligent Edge. With a strong presence in digitized factories, mobility, and digital healthcare, we're committed to combatting climate change and reliably connecting humans and the world.

As a global company with over 25,000 employees and 125,000 customers worldwide, we're dedicated to ensuring today's innovators stay Ahead of What's Possible.

The CSI Team

The CSI team at Analog Devices is responsible for leading the market in technology domains with highly differentiated sensing and signal processing solutions. Our areas of expertise include Capacitive Sensing, Optical Image Stabilization, and Optical sensing, driving growth in our portable Consumer business.

We're committed to delivering sustainable growth and offer a great opportunity for continuous career development as part of a highly motivated and supportive team.

The Position

We're seeking an enthusiastic physical design engineer for our Consumer Product development team in Valencia. The team is responsible for developing mixed signal subsystems for next-generation consumer products, including digital signal processing data paths and embedded microprocessor systems combined with high-precision analog subsystems.

This is an excellent opportunity to employ state-of-the-art design physical design methodologies, gain exposure to a wide range of technical disciplines, and experience career growth.

Requirements
  • B.Tech/M.Tech. in EE/ECE with 8+ years of experience in digital implementation.
  • Strong knowledge in Floor planning, place and route, CTS, STA, ECO methodology, Power analysis, and Physical design verification.
  • Broad experience in synthesis and timing constraints.
  • Experience with 40nm digital implementation is essential.
  • Scripting skill and experience using languages such as Tcl, SKILL, and Perl.
  • Knowledge of the state-of-the-art implementation tools. Cadence tool experience preferred.
  • Experience working with Perforce/Methodics for versioning.
  • Knowledge of CPF/UPF methodology is an added advantage.
  • Knowledge of Cadence virtuoso tool is an advantage.
  • Knowledge of foundry rules and ability to produce tape-out ready GDS2 database is a plus.
  • Technical ownership and hands-on expertise needed. Should be able to step in and take responsibility of implementation tasks when needed.
  • Strong inter-personal, teamwork, and communication skills are required.
Responsibilities
  • Floorplan development, power/ground distribution, and clock distribution.
  • Logic synthesis, cell placement, and interconnect routing.
  • Equivalence-checking, timing closure, and physical verification (LVS, DRC).
  • Strong collaboration with RTL designers to solve challenging problems.

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