Senior Dsp& Ia Digital Communications Design

hace 6 meses

Tres Cantos Madrid provincia, España Thales A tiempo completo

Location: Madrid Tres Cantos, Spain

A Joint Venture between Thales (67%) and Leonardo (33%), Thales Alenia Space is a global space manufacturer delivering, for more than 40 years, high-tech solutions for telecommunications, navigation, Earth Observation, environmental management, exploration, science and orbital infrastructures. Thanks to our diversity of skills, talents and cultures, our customers (governments, institutions, space agencies, telecommunications operators), therefore have Space to Connect, Secure & Defend, Observe & Protect, Explore, Travel & Navigate.

Thales in Spain is a leader in technological solutions applied to Defence, Aeronautics, Security, Transportation and Space and, furthermore, is a global centre for excellence in Space, Security of Critical Infrastructures and Transportation. With a turnover of €320 million and a staff of 1,200, it exports approximately 40% of its total production principally to the Middle East, North Africa and Latin America.

**Education**:

- Master degree in Telecommunication Engineer (MSc), or equivalent, with firm background on Signal and Systems theory, digital communications and electronics

**Experience**:

- More than 10 years-experience in designing and development of SDR/digital communication architectures and algorithms applied to communication systems: modulation schemes, error correction coding, characterisation of communication links (channel distortion, EVM, BER, FER).
- More than 10 years of Experience in Digital Signal Processing Design for Up/Down conversions, digital filtering, suppressed/reduced carrier and spread-spectrum digital modulation/demodulation, coding/decoding, NCO, interference mitigation, etc.
- More than 10 years of Experience in designing and implementation of Signal Processing Algorithms (DSP), specification and evaluation of FW processes and algorithms for FPGAs or Microprocessors. A deep understanding of floating-point to fixed-point algorithm translation is a must.
- More than 10 years of Experience in debugging the FW- FPGA solution or C-Microprocessors solution at laboratory during HW-FW integration.
- Previous experience on Artificial intelligence and Machine learning algorithms applied to image processing and communications systems.
- Profound knowledge of FPGA, microprocessors and System on Chip devices (MPSoC, RFSoC).
- Use of test instrumentation: Spectrum Analysers, Network Analysers, Signal Analyzers, Logic Analyzers, Data Patterns Generators, Oscilloscopes, BER meters

**Tools**:

- Simulation software: MATLAB, Simulink, HDL Coder,
- Software Programming: C/C++, Python.

**Languages**:

- Proficient in English.
- Spanish knowledge recommendable

**Skills**:

- Team work, improvement spirit, pragmatic, results oriented, dynamic, accountable and proactive.
- Capable of having an overall vision of the solution and to focus on each individual component.
- Motivated to learn new technologies, and space-business processes and tools
- Capable to solve engineering problems within risk, cost & schedule constraints
- Valued Experience in Agile methodology.
- Willing to face challenges
- Ability to work effectively in a multi-cultural environment

**Added Value**:

- Knowledge of VHDL simulation (pre-synthesis & post-layout verification)
- Experience in space sector. Knowledge of space programs design rules and standards.
- Third language: French

**Tasks**
- _ To evaluate the customer specification and perform the flow-down of these requirements (up/down conversions, digital filtering, modulation/demodulation, coding/decoding, NCO, interference mitigation) to VHDL specification_
- _ To generate the MATLAB/Simulink models of the processing blocks when needed to detail the VHDL requirements, taking into account the translation from floating-point to fixed-point._
- _ To review the Design, Development and Validation Plan of the FPGA according to the FPGA requirements or C-Microprocessors solution._
- _ To participate in the C/FW-HW integration tests in order to ensure the correct implementation of the FPGA design with respect to the customer specification._
- _ To participate in the unit design reviews with customers in an international environment as leader of the unit data processing performances._

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