Staff Engineer, Design Verification Engineering

hace 4 semanas

Valencia, España Analog Devices A tiempo completo

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.

The Group

The charter of ADI’s CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Today these technology areas include Capacitive Sensing, Optical Image Stabilization and Audio that drive growth in our portable and non-portable consumer business. As part of our global operation and expanding business needs, we are now seeking to fill key roles in defining, developing, and verifying digital systems for this key market area. This would scan the entire development cycle from concept phase, through design, verification, implementation, and release of products to customers. The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products

**Responsibilities**:
Based in Spain (Valencia), this position will be responsible for contributing to:

- Verification of complex designs and sub-systems using leading edge verification methodologies
- Contribute and Influence the decisions on methodologies/strategies to be adopted for the verification. Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog.
- Architect the testbench and develop in UVM or Formal based verification approaches.
- Proficient in developing unit and SoC level test benches using UVM. Integrate the block testbench in chip-level UVM environment and verify integration.
- Define test-plans, tests and verification methodology for block/chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
- Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
- Continuous interaction with analog co-sim and firmware team.
- Managing scripts written in TCL/Perl/Python for different verification aspects.
- Coding up in C tests on M3 Series Cortex based products.
- Technically mentor and guide junior verification engineers on SoC Verification.

**Qualifications**:

- Bachelor's or master’s degree, in Engineering (Electronic Engineering) or equivalent
- Excellent debugging and analytical skills.
- 5-10 years in ASIC design verification.

Additional Preferred Qualifications
- Experience with HW emulation or FPGA prototyping
- Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing.

LI-CO1
- For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process._
- Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group._

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

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