My client is looking for a Senior Functional Verification Engineer to join their dynamic Verification Team. In this role, you will be at the forefront of ensuring the correctness and functionality of complex digital designs at the Register Transfer Level (RTL). Using advanced verification methodologies and tools, you will play a pivotal role in validating designs that shape the future of technology. They offer a flexible and supportive work environment, competitive compensation, and a culture of continuous learning and growth. Lea atentamente toda la información sobre esta oportunidad y luego utilice el botón de solicitud de abajo para enviar su CV y su candidatura.Responsibilities As a Senior Functional Verification Engineer, you will: Develop and execute verification plans to ensure the functionality and correctness of digital designs Utilise SystemVerilog and UVM methodologies to validate designs at the block, sub-system, and top levels Perform both formal and dynamic verification to identify and resolve design issue Leverage scripting languages (Python, Perl, Bash, TCL) Utilise simulation tools and regression methodologies to validate designs Manage version control using tools like Git and SVN Troubleshoot and resolve complex technical challenges with a keen eye for detail Qualifications To excel in this role, you should have: A Master's or PhD in a relevant field Significant industry experience in functional verification Expertise xohynlm in SystemVerilog and UVM methodologies Strong knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools Hands-on experience with simulation tools and methodologies A solid understanding of formal and dynamic verification techniques If you're ready to take your career to the next level and make a significant impact in the world of digital design, we want to hear from you. Apply today and become a part of this innovative team.