RISC-V Manager

Working for a cutting edge semiconductor company, based in Barcelona I have an exciting opportunity as HW Engineering Manager.You will be tasked with managing a team who are developing a RISC-V SOC.Applicants can come from an architecture, digital design or verification background.MUST HAVE - Deep understanding of ASIC, FPGA and SOC development processes.Must have experience:Degree / Masters / PhD in electronics / micro-electronics, physics or similar field10+ years' experience of full chip design and deliveryTech lead / team leadership / team management - circa 10+ peopleASIC / FPGA digital design - verilog, system verilog, VHDLSignificant experience of delivering: digital chips and complex processor based SOCsCPU / GPU / RISC-V / MIPS / ISA / x86 processor knowledgeSOC design, architecture, integrationSOC interconnects - NOC IP, AXI, AMBA protocols etcStrong understanding of high-speed digital products; SerDes, PCIe, ethernet, DDR, DRAM, HBM memoriesFunctional verification UVMFormal verification - jasper gold, OneSpin, VC Formal, Mathworks, GitHubConfident knowledge of the whole ASIC / SOC / chip design flowAbility to demostrate multipe tape-out deliveries (silicon right first time etc)Bonus / preferred skills:VPU (scalar, vector, matrix)FPU - floating point algorithms / computer arithmeticCompiler architectureCompute architecureSystem architecureperformance / modelling