Principal Digital Design Engineer

hace 6 días

Valencia, España ams R&D Spain S.L. A tiempo completo

The CSA division supplies sensors that bridge the gap between the world we live in and the digital world of machines. By converting physical signals - heartbeats, sounds, light waves - into data, we enable robots, cars and other devices to interact with people and improve our world. What drives CSA is a relentless desire to contribute to technology and have a meaningful impact on the world. This business thrives on solving complex problems and partnering with global leaders at the forefront of technological advancement. Our goal: to push the boundaries of sensor technology and empower innovators to make the world smarter, healthier and happier.
- Architect and design high‑quality digital solutions for CMOS ICs, contributing to specifications and delivering all required technical documentation.
- Develop RTL designs using SystemVerilog, including formal verification, CDC analysis, synthesis and definition of timing constraints.
- Support backend implementation, guiding physical design, static timing analysis and DFT activities, and evaluating power consumption and power integrity.
- Implement and verify ECOs on existing designs to ensure functional and timing correctness.
- Provide technical leadership for digital design activities, collaborating closely with the project technical lead and project manager.
- Create and patent new IP, contributing to innovation and long‑term technology development.
- Mentor and develop engineering talent within the Medical Imaging group, fostering technical growth and best practices.
- University degree in Electronics Engineering or a related field.
- 7+ years of experience in digital design, with proven hands on involvement in complex, relevant projects.
- Strong proficiency in RTL design using HDLs such as Verilog or VHDL for integrated devices; experience with FPGA based design is considered an advantage.
- Familiarity with digital design flow tools, including linting, CDC/RDC analysis, synthesis, static timing analysis (STA), DFT and logical equivalence checking (LEC).
- Understanding of advanced digital verification methodologies, with experience in UVM or similar frameworks viewed as a plus.
- Strong analytical mindset, capable of solving complex technical problems and efficiently debugging simulation related design issues.
- Collaborative and team oriented, consistently meeting deadlines and adhering to disciplined development processes.
- Highly committed and adaptable, demonstrating ownership, initiative, and a “make it happen” attitude.
- Company focused team player, prioritizing what best serves the organization and project goals.
- Clear and effective communicator, with strong proficiency in English. Knowledge of Spanish is considered an advantage.

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