Sr. Design Verification Engineer

hace 7 días

Barcelona, España Esperanto.ai A tiempo completo

**Responsibilities**:

- Technical ownership of the validation of various functional blocks of the CPU
- Developing testplans and driving reviews of the plans with the design team and architects
- Developing validation content like test benches, directed and constrained random assembly tests, and functional coverage
- Closing functional/code coverage for assinged functional blocks

Minimum Qualifications
- BS in EE or related technical field
- +5 years of experience in CPU/SoC validation
- Knowledge of CPU and SoC architecture
- Knowledge of FP processing
- Knowledge of high-level verification flow methodology (testplan development, test generation and debug, coverage analysis and closure)
- Experience with SystemVerilog and UVM
- Experience with C/C++ and assembly
- Experience with Perl, Python, TCL or other scripting languages
- Ability to clearly communicate across teams with multidisciplinary backgrounds
- Business fluent English
- Experience with FPGA Prototyping and familiarity with Synopsys Zebu emulator a plus

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