Rtl Verification Engineer

**We are now hiring a RTL Verification Engineer / FPGA Verification Engineer***:
**Clue**'s motto is creating simple solutions to big problems.

We research, design, and produce innovative electronic systems for the aerospace industry. Our main areas of expertise are safety-critical embedded system design, artificial intelligence, and high-performance computing for avionics. We collaborate in R&D projects with global key players and develop disruptive products from scratch.

We are committed to excellence and efficiency in everything we do. We are aware of the importance of generating creative ideas and meeting deadlines, accepting new challenges and facing the problems we may find. To this end, we are in continuous learning and managing change.

**What is the job about?**:
To do this, you will lead verification decisions for IP Cores and full FPGA designs used in Clue’s computer boards.

You will also participate in the definition of processes and methodologies for the RTL team related to verification, and you will collaborate with the integration of these verification processes in our CI/CD system.

You will participate in the definition of Verification Plans, Test cases and Procedures, implement RTL simulation testbenches, formal verification testbenches and scripts for verification in HW target. You will also elaborate Test Results documents and maintain traceability between Requirements, Test Cases and Test Results.

You will work in a collaborative environment where you will participate in multiple reviews of requirements, test cases, test results, etc, where you will collaborate closely with other colleagues to debug Clue RTL designs and where you will help with the training of other colleagues with less experience in verification.

**What will you do?**:
Development of Verification Plans
Development of Test Cases and Procedures
Implementation of RTL simulation testbenches
Implementation of RTL formal verification test benches
Development of scripts for RTL verification on HW target
Debugging of RTL designs
Definition of processes and methodologies for the RTL team related to verification
Integration of verification processes in RTL CI/CD system
Help with verification training of other members of the team

**What are we looking for?**:
Required:

- 4-8 years of relevant experience
- You are an expert using an HDL language (VHDL, System Verilog)
- RTL Verification is an essential part of your toolbox set (Directed test benches, formal verification, UVVM, verification on HW target)
- You have an excellent ability to create modular and reusable architectures
- You have experience developing Test Cases for Requirement based Verification
- You have worked under the guidance of design assurance standards (DO-254 or similar depending on the industry)
- You rather script something than do it twice (Python, TCL)
You are able to integrate new verification tools in a CI/CD system

Valuable
- You understand what formal verification is and how to use it
- You have experience in FPGA/ASIC design
- Using synthesis tools is second nature to you (Synplify, Vivado, Quartus II)
- You have built confidence in your Static Timing Analysis skills to the point that you excel at spotting and fixing timing issues

**What do we offer?**
***:

- Hybrid working: we'll expect you to go to our offices 1-2 days per month and travel occasionally to our offices in Málaga
- The role is expected to be filled between November and January, ideally in December.
- Full-time, permanent contract
- Private medical insurance
- 25 + 2 flexible vacation days
- Schedule flexibility
- Free Friday afternoons
- Permanent internal and external training
- Free coffee and snacks
- Healthy lunch served daily for the staff at the office (Monday-Thursday)
- Work with the cutting-edge technologies

***
**Which are the steps of the process?****:

- Talent Interview
- Technical Interview
- Management Interview

Need more information about these steps? Click here.