Research Engineer

**Job Reference**:

- 820_24_CS_Int_RE3-T1**Position**:

- Research Engineer - RTL Integration (RE3-T1)**Closing Date**:

- Friday, 31 January, 2025**Reference**: 820_24_CS_Int_RE3-T1**Job title**: Research Engineer - RTL Integration (RE3-T1)**About BSC**
- The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, was a founding and hosting member of the former European HPC infrastructure PRACE (Partnership for Advanced Computing in Europe), and is now hosting entity for EuroHPC JU, the Joint Undertaking that leads large-scale investments and HPC provision in Europe. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 1000 staff from 60 countries.

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We promote Equity, Diversity and Inclusion, fostering an environment where each and every one of us is appreciated for who we are, regardless of our differences.**Context And Mission**
- Applications are invited for an engineer in High Performance Computing (HPC) architectures at the Barcelona Supercomputing Center (BSC). BSC intends to pave the way to the future low-power European processor for Exascale in the context of multiple architecture initiatives, such as EPI, Lenovo, Intel and Zettascale Lab.**Key Duties**
- As an engineer on the Integration team, you will collaborate with a research team to develop, implement, and verify an HPC system based on RISC-V. Your role will involve working on cutting-edge device architectures, defining designs, implementing solutions, and conducting verification, as well as creating essential hardware and software components for system simulation and debugging.
- Design and Implement the components required to assemble a RISC-V-based HPC system that meets the specified performance targets, including on-chip peripherals.
- Analyze the performance of a RISC-V based HPC processor system, with special emphasis on the top-level integration of the constituent modules and the interconnection to external peripherals.
- Lead debugging sessions to resolve integration issues, including compatibility, specification, and performance concerns, and act as a bridge between the customer and BSC engineers by triaging issues and escalating them to the appropriate teams.
- Mentor junior engineers: provide guidance, share expertise, and foster their professional growth to enhance their technical skills and project contributions.

**Requirements**:

- Education
- MS in Computer Science, Computer Engineering or Electrical Engineering. Previous industrial experience is a big plus.
- Essential Knowledge and Professional Experience
- A minimum of 5 years of relevant experience
- Expertise on HDL programming languages (SystemVerilog, Verilog and/or VHDL) for FPGA prototyping and ASIC design as well as testbenches.
- Computer Architecture: microarchitecture, resource sharing in multicores, cache hierarchy, interconnection network.
- Low-level software languages such as C/C++ and Assembly Language.
- Working knowledge on Git, Makefile, tcl, bash, Python.
- Interconnect protocols, such as AXI, AMBA-CHI, NoCs.
- Team player.
- Additional Knowledge and Professional Experience
- Excellent written and verbal communication skills in English.
- RISC-V.
- Basic knowledge on FPGA.
- Leading skills.
- Competences
- Ability to take initiative, prioritize and work under set deadlines pressure.
- Ability to work independently and in a team.Ability to interact and build strong relationships with other research groups.**Conditions**
- The position will be located at BSC within the Computer Sciences Department
- We offer a full-time contract (37.5h/week), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, restaurant tickets, private health insurance, support to the relocation procedures
- Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
- Holidays: 23 paid vacation days plus 24th and 31st of December per our collective agreement
- Starting date: asap

**Applications procedure and process**
- A full CV in English including contact details
- A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered

At BSC we are seeking continuous improvement in our recruitment processes, for any suggestions or feedback/complaints about our Recruitment Processes, please contact recruitment [at] bsc [dot] es.

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**Deadline**O