Senior Cad Physical Design Engineer
hace 4 días
**Responsibilities**
- This is a technical hands-on senior position. You will lead the efforts of improving existing flows and define new flows.
- The role is collaborative. You will interact with senior leaders to develop best practices across all projects and disciplines in chip development.
- The CAD flow development will cover both front-end and back-end VLSI development.
- For front-end, this is static code analysis (i.e. lint style checking), regression testing, and tools to enable more efficient System Verilog development.
- For back-end it will be flows that enable automated synthesis and timing budgeting, plus place & route, extraction, static timing, power-EMIR, and finally physical verification.
**Qualifications**
- MS in Electrical Engineering or equivalent
- 10+ years’ experience working in all aspects of flow development.
- Experience with System Verilog development including static lint-style checkers and rules.
- Experience with advanced verification flows. You will work closely with the Design Verification team to develop and automate test building, simulation execution, and regression infrastructure. Experience with continuous integration is very valuable.
- Experience with timing budgeting and constraint management for both synthesis and STA.
- Experience with advanced Physical Design flows including place & route, static timing analysis (STA), logic equivalence checking (LEC), EMIR, and LVS/DRC.
- Experience managing a large compute farm, EDA tools installation and licensing.
- Experience with leading edge technologies and chip development flows (ideally 7nm moving into 5nm). This should include multiple tapeouts of hierarchical SOC’s.
- Exposure to UPF and low-power design techniques
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