Mixed-Signal Digital Design Engineer Lead
hace 2 meses
Mixed-Signal Digital Design Engineer Lead
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world—come join our team and see how YOU can make a difference.
Job Summary:
A Mixed-Signal Design Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.
Essential Functions:
Lead, supervise, mentor and train the MPS Mixed-Signal Design Team
Supervision of multiple projects to meet the different quality metrics, deliverables and the schedule
Be part of the Mixed-Signal Design recruitment process
Analog and Mixed-Signal Design, Verification and Validation for projects
Analog-Digital Interface Definition and Documentation
Behavioral Modelling of Analog Blocks. Analysis to verify architectural choices and trade-offs
Analog and Mixed-Signal IP Definition, Development, Integration and Verification
Layout Design
Analog and/or Digital Mixed-Signal simulations and debugging
Assist the Digital Design Team with Timing, Input/Outputs and DFT Constraints
Post-Silicon Validation and Characterization support
Close interaction and collaboration with Analog Design, Analog Layout, Digital Design Engineers, Digital Verification and Digital Physical Engineers
Qualifications:
BSEE + 12 years of experience, MSEE + 8 years of experience in ASIC Mixed-Signal design
Ability to work independently and collaborate with other teams/departments
Leadership abilities to handle multiple projects and a small group of Mixed-Signal Designers
Solid knowledge of the full ASIC development and Silicon fabrication process
Strong background in transistor level and analog/mixed circuit design
Solid Understanding of device mismatches, noise, linearity and other analog effects
Experience in Layout design and knowledge of best-practice techniques
Experience with simulation tools such as spectre, hspice, and MATLAB
Proficient with Cadence circuit design tools like ADE-L and ADE-XL
Understanding and experience in running complex simulations such as Monte-Carlo, noise simulations and stability analysis
Experience running DRC and LVS using Calibre, ICV, etc.
Experience running Verilog-AMS mixed-mode simulations
Verilog, System Verilog and Verilog-A coding skills for behavioral modelling
Knowledge of DFT Techniques such as SCAN, LBIST, ABIST and IDDQ
Knowledge of STA and Mixed-Signal Timing and Input/Output Constraints for Syn and P&R
Excellent written/verbal communication skills and strong teamwork/collaboration
Knowledge/Experience with the following is a plus:
Automotive and ASIL Standards
Knowledge of power management industry/applications
I2C, I3C, SPI, USB, PMBUS
GitLab and Cliosoft SOS
Location:
Barcelona, Spain
Monolithic Power Systems, Inc. (MPS) strives to build and maintain a culture of diversity, equity, and inclusion. We recognize that diverse voices and ideas make our company and our products stronger, and we believe that our employees benefit when they are immersed in an inclusive culture of teamwork, fairness, and tolerance. We are mindful that creating an inclusive workplace that supports all employees is critical to our success.
Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.
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