Digital Ic Verification Engineer
hace 1 semana
Job DescriptionJoin a thriving environment tasked with delivering new and disruptive technologies. We are looking for a Digital IC Verification Engineer with hands‑on experience using Cadence verification tools to verify complex digital ICs and SoCs. The role focuses on building high-quality verification environments, executing simulation and coverage‑driven verification, and ensuring design correctness prior to tape‑out.Key ResponsibilitiesDevelop verification plans from design specifications and micro‑architecture documentsBuild and maintain SystemVerilog/UVM testbenches using Cadence verification flowWrite directed and constrained‑random tests to validate RTL functionalityDevelop and integrate SystemVerilog Assertions (SVA)Execute simulations and regressions using XceliumDebug functional failures using SimVision and waveform analysisPerform functional, code, and assertion coverage using Integrated Metrics Center (IMC)Achieve coverage closure and support verification sign‑offCollaborate with design engineers to identify, debug, and resolve RTL issuesPerform CDC/RDC analysis using Cadence JasperGold or Conformal CDC (if applicable)Support low‑power verification using UPFParticipate in design and verification reviews and provide sign‑off reportsQualificationsBachelor's or Master's degree in Electrical / Electronics / Computer EngineeringStrong understanding of digital design fundamentals (timing, FSMs, pipelines, clocking, resets)Proficiency in SystemVerilog and UVMHands‑on experience with Cadence Xcelium simulation toolExperience with IMC for coverage analysis and closureFamiliarity with SimVision for debug and waveform analysisUnderstanding of assertion‑based verification (SVA)Knowledge of coverage‑driven verification methodologyNice To HaveExperience with Cadence JasperGold (formal verification, CDC, RDC)Familiarity with low‑power verification using UPFExperience verifying standard protocols (AXI, AHB, APB, PCIe, etc.)Knowledge of Cadence VIPsScripting experience in Python, Perl, or TCLExperience with SoC‑level verification, emulation, or PalladiumCadence Tools & TechnologiesXcelium – Simulation and regressionSimVision – Debug and waveform analysisIMC – Coverage analysis and closureJasperGold – Formal verification, CDC/RDCVIP Catalog – Protocol verification IPPalladium – Emulation (optional)Senior: 7+ years (verification architecture, sign‑off responsibility)Strong debugging and analytical skillsClear written and verbal communicationAbility to work effectively in cross‑functional teamsWhy Join UsAt The TMRW Foundation SILICON – you will be part of a dynamic and innovative team that is dedicated to building cutting‑edge technologies. We offer a collaborative and inclusive work environment where your contributions will make a significant impact.You can send your CV to ******.Additional InformationSeniority level: Mid‑Senior levelEmployment type: Full‑timeJob function: Information TechnologyIndustries: Computer and Network SecurityLocation: Santa Cruz de Tenerife, Canary Islands, SpainReferrals increase your chances of interviewing at TMRW by 2x#J-18808-Ljbffr
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Digital Ic Verification Engineer
hace 1 semana
Santa Cruz de Tenerife, España TMRW A tiempo completoJob DescriptionPor favor, verifique que tiene el nivel de experiencia y las cualificaciones adecuadas leyendo la descripción completa de esta oportunidad a continuación.Join a thriving environment tasked with delivering new and disruptive technologies. We are looking for a Digital IC Verification Engineer with hands‑on experience using Cadence...
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Digital Ic Verification Engineer
hace 1 semana
santa cruz de tenerife, España TMRW A tiempo completoJob Description Join a thriving environment tasked with delivering new and disruptive technologies. We are looking for a Digital IC Verification Engineer with hands‑on experience using Cadence verification tools to verify complex digital ICs and SoCs. The role focuses on building high-quality verification environments, executing simulation and...
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