UVM Developer

Project description

We are looking for a seasoned UVM Developer to lead our efforts in creating robust verification environments for complex semiconductor devices. This role demands deep expertise in using cutting-edge simulation tools, primarily Xcelium, to drive functional simulations and comprehensive documentation. The successful candidate will play a pivotal role in enhancing our product reliability and accelerating our time-to-market.

Responsibilities

1. Develop and maintain UVM test benches for advanced verification of digital designs.
2. Utilize simulation tools such as Xcelium to perform functional simulations, ensuring design integrity and performance.
3. Optimize existing verification environments to improve efficiency and effectiveness of simulations.
4. Work closely with design and system engineering teams to understand requirements and implement verification strategies accordingly.
5. Analyze simulation results, identify and troubleshoot discrepancies to ensure product specifications are met.
6. Document verification processes and results thoroughly to support design validation and future references.

SKILLS

Must have

1. Proven expertise in Universal Verification Methodology (UVM) for creating and managing test benches.
2. Proficiency with simulation tools like Xcelium or similar environments for functional simulation of digital designs.
3. Strong analytical skills to interpret complex design specifications and simulation results.
4. Excellent problem-solving abilities, with a keen attention to detail in troubleshooting and optimizing verification environments.

Nice to have

1. Experience with other verification languages and methodologies such as SystemVerilog, OVM, or VMM.
2. Familiarity with ASIC design flow and constraints.
3. Prior experience in the semiconductor or electronics manufacturing industries.