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Senior ASIC Lead: RTL to Tapeout with FPGA Prototyping
hace 2 semanas
A leading microelectronics company in Barcelona seeks a highly experienced professional to lead ASIC developments. This role combines technical leadership with collaboration with public research centers and involves responsibilities from architecture and RTL design to silicon validation. Ideal candidates will have 15+ years of experience in ASIC development, a Master's degree in Electronics Engineering, and expertise in digital design languages and FPGA prototyping. A competitive remuneration package and flexible work conditions are offered.#J-18808-Ljbffr
