Emulation-Prototyping Senior Engineer

We are actively seeking a Silicon Design Framework and Emulation‑Prototyping Engineer to join our dynamic and growing Hardware Design team. The mission of the role is to enable fast, reliable, and scalable hardware‑software co‑design by developing and maintaining design frameworks, emulation platforms, and prototyping environments that accelerate silicon validation and system bring‑up. Key Responsibilities Develop and implement emulation & prototyping strategies based on product goals and KPIs. Enable accelerated HW validation, compliance testing, and stress testing using emulation platforms. Enable hardware‑SW‑driven software development and debugging on emulation and prototyping platforms. Contribute to the definition and maintenance of virtual platforms for SW development, co‑emulation (hybrid platforms), SW‑driven HW verification, and architectural exploration. Develop and maintain emulation, prototyping and virtual prototyping frameworks to enable the performance and power analysis of the SoC. Required Qualifications At least 5 years of past experience developing in SoC design and delivering hardware products or solutions. HDL and HVL languages (Verilog, SystemVerilog, C/C++, SystemC, VHDL). Familiarity with UVM methodology and testbench construction, functional coverage, Verilog assertions, and verification IPs. Experience with EDA tools for digital simulation (Questa, VCS, Xcelium) and debugging (Visualizer, Verdi, Verisium).  Direct experience with commercial emulation platforms (Synopsys Zebu EP1/2, Cadence Palladium Z1/Z2, Siemens Veloce Strato+) or prototyping platforms (Synopsys HAPS‑80/100, Cadence Protium X1/X2, Siemens Primo, Primo CS, ProFPGA, ProFPGA CS) is appreciated. Direct experience in developing/setting‑up custom or commercial transactors for interfacing SystemVerilog UVM testbench or SystemC TLM virtual platforms with emulation platforms is appreciated. Direct experience setting‑up emulation and prototyping platforms for SW debugging through physical or virtual JTAG interface is appreciated. Familiarity with system/functional modeling languages (C, C++, SystemC TLM LT/AT). Direct experience in constructing virtual platforms for SW development, architectural exploration, co‑emulation with commercial virtual prototyping platforms (Synopsys Platform Architect, Virtualizer; Cadence Helium; Siemens NextGen/Vista) or open‑source frameworks like Gem5. Experience in processor compliance testing, ISS simulators & reference models (Spike, riscvOVPsim), stress tests, benchmarking and other commercial processor‑centric functional verification suites (Sting, ImperasDV) is appreciated. Familiarity with high‑performance coherent on‑chip & chiplet‑to‑chiplet communication protocols (AXI‑ACE, CHI, CXL), interfaces (PCIe, UCIe), debug interfaces/protocols (JTAG, ATB, TPIU, etc.), cache coherency, and interfaces to high‑performance memory systems (HBM controller/PHY) is appreciated. Experience with RISC‑V toolchain and ISA is a plus. MS in EE, CE, CS or a related technical discipline. What do we offer? Join an innovative team and experience company growth. We invest in our employees and provide opportunities to grow and develop your career. Enjoy a hybrid work environment and a flexible schedule. We offer a remuneration that values your experience. The position will have its base in Barcelona , Spain. We are looking for outstanding people willing to join our mission to change this industry and help to build a better world. If you feel identified with Openchip, a competitive compensation package in a flexible work scheme that will help you keep a balance between your personal and professional life. At Openchip & Software Technologies S.L. , we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity. #J-18808-Ljbffr