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Senior Analog Design Engineer
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Madrid, España Beagle A tiempo completoROLE: Senior Mixed-Signal IC Design Engineer LOCATION: Madrid, Spain SALARY: Negotiable DURATION: Permanent An exciting opportunity to join a high-tech R&D team in Madrid, developing advanced analog and mixed-signal ICs in leading-edge CMOS technologies. This role offers the chance to work across the full design flow — from concept and system-level...
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Senior Analog/Mixed Signal IC Design Engineer
hace 3 semanas
Senior Mixed‑Signal IC Design Engineer Madrid, Spain | Permanent | Salary: Negotiable Join a cutting‑edge R&D team in Madrid developing advanced analog and mixed‑signal ICs in leading‑edge CMOS technologies. This is an opportunity to work across the full IC design flow — from concept and system‑level definition to silicon validation — contributing to innovative products used in next‑generation communication, sensing, and optoelectronic systems. What You’ll Do Specify and design analog and mixed‑signal blocks (ADCs, DACs, PLLs, data interfaces, optoelectronics, etc.). Own the AMS design flow from schematic to full verification in sub‑nanometer CMOS processes (65 nm, 28 nm and below). Define layout guidelines, collaborate with layout engineers, and review designs to ensure integrity and performance. Partner with test engineers to define and execute test plans, analyze lab data, and correlate with simulations. Develop behavioral models of AMS blocks for system‑level and mixed‑signal simulations. Support integration of analog subsystems into complex SoCs with significant digital content. Contribute to R&D innovation, explore new architectures, and support patent and product concept development. Present design progress and results in technical reviews and team meetings. What You’ll Bring MSc or PhD in Electronics, Electrical, or Computer Engineering (or related field). 5+ years of hands‑on experience in analog and mixed‑signal IC design. Proven track record of silicon‑proven designs, from specification to productization. Expertise in full‑custom analog IP design in advanced CMOS nodes (65 nm/28 nm or below). Proficiency with EDA tools (Cadence, Synopsys) for AMS design and verification. Strong knowledge of analog layout techniques and ability to review layout work. Excellent communication skills in English (written and verbal). #J-18808-Ljbffr
