Digital Ic Verification Engineer

hace 5 días

Huelva, España Thisistmrw A tiempo completo

Digital IC Verification Engineer at TMRWJoin a thriving environment tasked with delivering new and disruptive technologiesKey ResponsibilitiesDevelop verification plans from design specifications and micro-architecture documentsBuild and maintain SystemVerilog/UVM testbenches using Cadence verification flowWrite directed and constrained-random tests to validate RTL functionalityDevelop and integrate SystemVerilog Assertions (SVA)Execute simulations and regressions using XceliumDebug functional failures using SimVision and waveform analysisPerform functional, code, and assertion coverage using IMC (Integrated Metrics Center)Achieve coverage closure and support verification sign-offCollaborate with design engineers to identify, debug, and resolve RTL issuesPerform CDC/RDC analysis using Cadence JasperGold or Conformal CDC (if applicable)Support low-power verification using UPFParticipate in design and verification reviews and provide sign-off reportsQualificationsBachelor's or Master's degree in Electrical / Electronics / Computer EngineeringStrong understanding of digital design fundamentals (timing, FSMs, pipelines, clocking, resets).Proficiency in SystemVerilog and UVM.Hands‑on experience with Cadence Xcelium simulation tool.Experience with IMC for coverage analysis and closure.Familiarity with SimVision for debug and waveform analysis.Understanding of assertion‑based verification (SVA).Knowledge of coverage‑driven verification methodologyNice To HaveExperience with Cadence JasperGold (formal verification, CDC, RDC)Familiarity with low‑power verification using UPFExperience verifying standard protocols (AXI, AHB, APB, PCIe, etc.)Knowledge of Cadence VIPsScripting experience in Python, Perl, or TCLExperience with SoC‑level verification, emulation, or PalladiumCadence Tools & TechnologiesXcelium – Simulation and regressionSimVision – Debug and waveform analysisIMC – Coverage analysis and closureJasperGold – Formal verification, CDC/RDCVIP Catalog – Protocol verification IPPalladium – Emulation (optional)Senior: 7+ years (verification architecture, sign‑off responsibility)Strong debugging and analytical skillsClear written and verbal communicationAbility to work effectively in cross‑functional teamsYou can send your CV to ******.#J-18808-Ljbffr

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