FPGA Senior Engineer

ARQUIMEA Madrid, Community of Madrid, Spain FPGA Engineer (Space and Defense)Join ARQUIMEA, a technology company operating globally, offering innovative solutions in aerospace, defense & security, big science, and fintech. We are looking for a Digital Hardware / FPGA Design Engineer with solid experience in the design and verification of digital circuits for FPGAs, ASICs and SoC devices, preferably in high‐reliability sectors such as space, aerospace or defense. Responsibilities Specify, architect, implement and verify digital hardware for embedded systems in space and defense applications. Collaborate with multidisciplinary teams to develop FPGA IP cores, ASICs, standard ICs and associated software for space and defense programs. Define the architecture of digital integrated circuits, SoCs and FPGA IPs, including feasibility analyses and design trade‐offs. Perform front‐end design and verification of digital modules at RTL level, from requirements capture to sign‐off. Model and simulate complete solutions to evaluate and optimize digital circuits. Plan, execute and document verification, testing and debugging activities on FPGA prototypes. Participate in the analysis and specification of digital subsystems and lead or contribute to design reviews. Collaborate with validation and test teams during bring‐up and qualification of ICs and IP blocks. Define the firmware/software architecture for SoCs embedded in FPGAs and coordinate its integration with the digital hardware. Create and maintain clear, accurate and comprehensive technical and project documentation. Analyze alternative technical solutions using quantitative metrics and support technical decision‐making. Qualifications University degree in Electrical / Electronic Engineering, Telecommunications Engineering or Physics. Master's degree and/or PhD in a related field will be valued. Solid academic background in digital circuit design and FPGA‐based systems. Solid experience in HDL front‐end design (VHDL and/or Verilog). Hands‐on experience with FPGA design tools (e.g. Xilinx Vivado, HDL Author or similar). Strong understanding of digital design principles, including logic design, state machines and data paths. Proficiency in using simulation and verification tools to evaluate digital designs (e.g. ModelSim, Questa). Strong background in verification activities (testbenches, functional coverage, regression testing, etc.). Knowledge of computer architectures for SoC integration, in particular ARM, RISC‐V and MicroBlaze. Experience preparing specifications and test plans for FPGAs, including architecture design and functional allocation between software and FPGAs. Experience with revision control tools (e.g. Git). Knowledge of MIL‐STD and ECSS standards applicable to firmware/software development. At least 5 years of professional experience in digital hardware / FPGA design, preferably in space, aerospace, defense or other high‐reliability sectors. Proficient in English (written and spoken). Spanish is a plus. Open‐minded and ready to be challenged in a fast‐paced, multidisciplinary and multinational environment. Eligible to work in the EU and able to travel to the US when required. Eligible to obtain a security clearance from the Spanish Ministry of Defense. Preferred Additional Experience Experience in digital ASIC design. Work experience with MATLAB and/or other high‐level modelling languages. Experience or knowledge in cryptographic implementations and hardware security, including side‐channel analysis and/or fault‐injection techniques. Experience automating unit, integration and HIL testing and setting up CI/CD pipelines. Hands‐on experience with laboratory electronic hardware and instrumentation. Experience in back‐end / physical design of digital ASICs and FPGAs, including Synopsys and/or Cadence digital implementation tools. Hands‐on experience in embedded processor programming (C and assembly). Experience with communication interfaces such as Ethernet, MIL‐STD‐1553, CAN and SpaceWire. Experience in reliability and radiation‐effects mitigation techniques for space applications. Ability to lead a small technical team or work package when needed. The position is based at our offices in Madrid city, located at Calle Serrano Galvache, 56. Seniority Level Mid‐Senior level Employment Type Full‐time Job Function Engineering and Information Technology Industries Space Research and Technology Referrals increase your chances of interviewing at ARQUIMEA by 2x En ARQUIMEA valoramos la diversidad y la inclusión. No discriminamos por motivos de raza, color, religión, género, orientación sexual, identidad de género, nacionalidad, edad, discapacidad u otros factores protegidos por la ley. Todos los candidatos serán considerados en igualdad de condiciones en base a sus habilidades y experiencia. #J-18808-Ljbffr