Chief ASIC Design Engineer
hace 6 días
Epsilonr seeks an experienced Chief ASIC Design Engineer to lead our team of Design Engineers at one of our European offices. This role requires on-site presence; remote options are not available.
About the RoleThis position involves overseeing all aspects of physical design and implementation, contributing to the establishment of physical design methodologies and workflow automation. As a key member of the design development team, you will focus on digital design implementation and verification of mixed-signal ICs using standard EDA tools.
Key Responsibilities- Lead physical design, development, and verification of digital/mixed-signal ICs.
- Drive chip and block floorplan/implementation, power and clock distribution, chip assembly, Place & Route (P&R), Static Timing Analysis (STA), and Layout vs. Schematic (LVS)/Design Rule Check (DRC) closure.
- Collaborate closely with digital/analog design teams for physical implementation and integration of custom analog blocks/interfaces/IPs.
- Contribute to building an automated RTL-to-PNR environment using high-level languages and DevOps-like services.
We seek a highly skilled and experienced individual with:
- An advanced degree in Electrical Engineering, Computer Science, or equivalent.
- Preferred 7+ years of experience in Physical Digital Design.
- Preferred 2+ years of experience in ASIC design, verification, or related work.
- Strong written and verbal communication skills in English, with a proven ability to collaborate effectively in a team environment.
- Ability to work independently, follow design specifications, and deliver tasks to meet project milestones with high quality.
- Solid understanding of ASIC development processes and digital design techniques.
- Proficiency in programming, scripting, and automation languages such as Perl, TCL, and Unix.
- Verilog/System Verilog coding.
- Synthesis, Logical Equivalence Checking (LEC), Clock Tree Synthesis (CTS), Design for Testability (DFT), RC Extraction, and STA closure across multiple process corners.
- Multipower domain, signal integrity, and power/IR drop analysis.
- Linting and Clock Domain Crossing (CDC) requirements.
- Functional and timing ECO methodologies, both manual and tool-driven.
- Physical Design Verification methodologies to debug LVS/DRC issues at chip/block level.
- Proficiency with industry-standard physical design tools, preferably Cadence or Synopsys.
- Experience in SOC design including microcontroller (uC) design (ARM/RISCV).
- Experience with digital on top designs using both bottom-up and top-down flows.
- Hierarchical STA for chip top designs and familiarity with advanced nodes below 16nm, FinFET.
We offer a competitive salary: €120,000 - €180,000 per year depending on location and experience.
About UsEpsilonr is a leading provider of innovative solutions for the electronics industry.
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