Senior Noc Engineer

hace 1 semana

Barcelona, España Akuaro Work SLU A tiempo completo

In 2023, Brussels approved 8.1 billion euros to boost the development of semiconductor technologies in Europe. The industry requires public aid to mobilize private investment, and in this chapter, it is expected to create 8,700 direct job opportunities. With this, microchips may become the backbone of Europe's industrial competitiveness in the coming years.

Our partner, a direct collaborator in the RISC-V architecture, is actively involved in a fierce battle against the "monopoly" ARM, leading companies like Google to consider shifting their future processors towards this architecture. This move addresses the growing need to incorporate AI into chips for mobiles, tablets, smartwatches, and ultimately any IoT device in the future. They are currently seeking to add talented individuals like you to their team.

Today, they boast highly specialized professionals in this field and have forged alliances with key industry partners, in addition to running their own training academy to nurture critical talent for their business. They are currently looking to onboard Senior Talent and Leads, and they invite you to be part of this exciting journey as a:
**NoC Design Engineer**, your role is pivotal in developing Network-on-Chip solutions within our semiconductor offerings. Collaborating with the NoC Design Team and closely engaging with other teams' proficient engineers, you'll contribute to crafting efficient, high-performance, and highly adaptable on-chip communication networks crucial for contemporary designs.

Job description (responsibilities):

- NoC Architecture - RTL Design
- Performance Optimization Desired

knowledge:

- Experience with the CHI and AXI* protocols
- Experience in extracting maximum Bandwidth with the lowest Latency
- Knowledge of Deadlocks/Livelocks
- Knowledge of Backend (physical design) concepts
- Proficiency in RTL design using Verilog or VHDL
- Knowledge of scripting languages (Python, Perl, Bash, TCL)
- Experience with EDA tools and synthesis
- Knowledge of revision control methodology and tools ( git, svn)
- Experience with basic block level testing
- Strong problem-solving skills and attention to detail

Preferred/Valued knowledge:
- Knowledge of RISC-V and RISC-V Vector Extension
- Knowledge of the JIRA tool
- Experience with high frequency designs
- Experience with ASIC and FPGA design is a plus

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