Senior Verification Engineer

hace 8 meses

Barcelona, España Akuaro Work SLU A tiempo completo

Our partner, a direct collaborator in the RISC-V architecture, is actively involved in a fierce battle against the "monopoly" ARM, leading companies like Google to consider shifting their future processors towards this architecture. This move addresses the growing need to incorporate AI into chips for mobiles, tablets, smartwatches, and ultimately any IoT device in the future. They are currently seeking to add talented individuals like you to their team.

Today, they boast highly specialized professionals in this field and have forged alliances with key industry partners, in addition to running their own training academy to nurture critical talent for their business. They are currently looking to onboard Senior Talent and Leads, and they invite you to be part of this exciting journey as a** Senior Verification Engineer**

Your responsibility lies within the Verification Team, where you'll play a vital role in validating the correctness and functionality of intricate digital designs at the Register Transfer Level (RTL) as per specifications. Utilizing advanced verification techniques and tools, you'll ensure the validation of designs with precision and accuracy.

**Job description (responsibilities)**:

- Verification Planning
- Testbench Development
- Verification Environment Setup
- Test Execution and Debugging
- Coverage Analysis
- Verification Methodologies

**Desired knowledge**:

- Proficiency in SystemVerilog and UVM

Knowledge of uArchitecture
- Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools

Experience of RTL Linting
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and sub-system or top level verification
- Experience with formal and dynamic verification
- Strong problem-solving skills and attention to detail
- Excellent communication and teamwork abilities

**Preferred/Valued knowledge**:
Knowledge of RISC-V and RISC-V Vector Extension
- Experience with GLS
- Knowledge of the JIRA tool
- Experience with ASIC and FPGA design
- Knowledge of C++

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