Digital Verification Engineer

hace 1 semana

Barcelona, España Monolithic Power Systems A tiempo completo

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry.We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures.At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers.Our portfolio of technology helps power our world --- come join our team and see how YOU can make a difference.Job DescriptionMPS is looking for a Digital Verification Engineer to join the Automotive BMS Product Line, focused on solving customers' challenges in Electric Vehicles (EVs).In this position, you will develop the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.ResponsibilitiesUVM and System Verilog based digital verification environment definition and developmentVerification IP (VIP) standardization, definition, development and documentationIntegrate VIPs into the digital verification environmentDevelopment of test plans to fully verify all digital requirements in project specificationDevelopment of coverage metrics and testcases to fully cover all test plan itemsDigital verification scripting and automationRegression infrastructure definition, development and managementClose interaction with Senior Digital and Analog Designers to develop VIP models and test casesLead and supervise digital verification tasks of multiple projectsAnalyze and debug test results, code coverage and functional coverageDigital verification estimation, planning and scheduling to meet tape-out datesQualificationsRequires BSEE/MSEE or Equivalent with emphasis in digital design/VLSI coursework5+ years of experience in both RTL and gate-level verificationProficient in digital verification industry languages (UVM, System Verilog) and standardsProficient level in DV skills: constraint randomization, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, and regression analysisSkilled with scripting languages such as C shell, Bash, TCL, Python or PerlStrong knowledge in verification of low power and multiple power domain designsExperience with digital design, including RTL coding in System Verilog, digital synthesis, timing closure and power estimationGood written/verbal communication skills and strong teamwork/collaborationSelf-motivated with attention to detailStrong analytical and problem-solving skills with ability to think outside the boxKnowledge/Experience in the following areas is a plus:Embedded designs and/or firmware developmentKnowledge of functional safety requirements for automotive parts (ASIL)Experience with Formal Verification tools such as Synopsys VC Formal or Cadence Jasper GoldLocationGermany – Munich, OttobrunnSpain – BarcelonaPortugal – Lisbon / PortoNetherlands – Enschede / NijmegenPhoenix, AZ

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