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Dft Senior Engineer
hace 2 meses
Openchip is a European Silicon Engineering Company, headquartered in Barcelona, Spain.
We aim to democratize the usage of Chips by developing Systems on Chip, SOCs, that combines RISC-V and accelerated chiplets for AI and HPC, everything interconnected with UCIe open interfaces.
Our technologies will provide value in multiple fields such as Artificial Intelligence, Security and Privacy, and Carbon Footprint Reduction.
We are willing to change the Silicon Industry and help to build a more sustainable world, where collaboration and openness are by default.
Our chips will be used in High Performance Computing, Autonomous Driving, Telecommunications, Personalized Medicine, Edge Computing, and Cloud.
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
We can offer you an exciting and accelerated career path in a multicultural and multinational environment where innovation, teamwork, and trust are in our DNA.
You will have the opportunity to learn from senior professionals, use the most advanced technologies to develop chips, and participate in one of the most relevant technological projects in the European Union.
We are actively seeking a Senior Design Manager to join our dynamic and growing Digital design team.
The Role: Responsibilities include but are not limited to: Work on design execution of silicon design Work on SoC DFT architecture and DFM concept Work on implementation and verification of DFT measures to meet product specifications and production requirements Work closely with cross-functional teams (design, production test, and qualification) to meet test requirements with effective DFT solutions Contribute to target coverage requirements for logic, memories, IO, and mixed-signal IPs Generate test patterns and support post-silicon ATE and QnR Qualifications: Minimum Qualifications: Degree/Masters in Electrical/Electronic Engineering Minimum 7 years and above in the area of IC digital design and more cycles of DFT and RTL design.
Good knowledge of ATPG scan, test controller, MBIST, and their implementation Good knowledge of HDL, synthesis, STA, top-level constraints, and scripting Good knowledge of EDA tools, e.g., VCS, TestMax DFT/ATPG/Advisor Strong analytical and problem-solving skills Preferred Qualifications: Experience working in a large corporation.
Knowledge of Network on chip architecture RiscV ISA/architecture and SOC based on this processor.
Knowledge of high-level (architecture) digital design language Knowledge of architecture analysis tools used for metric analysis.
Good knowledge of scripting languages: Perl, Python.
Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and/or schoolwork/classes/research.
We are looking for team players that focus on the outcome of the team above the individual needs, with respect and honest challenge.
Within- and cross-team collaboration at the technical level.
The ideal candidate should have a "can-do attitude", willing to solve any obstacle by themselves.
Self-starter and self-motivated.
What do we offer?
Join an innovative team and experience company growth.
We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.
Enjoy a hybrid work environment.
We also offer a flexible schedule.
We offer a remuneration that values your experience.
The position will have a base in Barcelona preferably.
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
If you feel identified with Openchip, please contact us.
We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.
At Openchip & Software Technologies S.L.
, we believe a diverse and inclusive team is the key to groundbreaking ideas.
We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.
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