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hace 5 días

Madrid, España Beagle A tiempo completo

ROLE:Senior Digital Design Engineer – Memory Subsystems LOCATION:Barcelona, Spain SALARY:Negotiable DURATION:PermanentWe are looking for a Senior Digital Design Engineer to design and develop high-performance memory subsystems for modern SoCs. You will work within the Memory Design Team and collaborate closely with other engineers to create efficient and robust memory architectures.Responsibilities: Define, design, and implement memory controllers and subsystems (DDR, HBM) Develop and verify RTL (Verilog or VHDL) for memory blocks Work with timing constraints and perform block-level testing Integrate memory IPs into SoC environments Collaborate with cross-functional teams to ensure coherency and high-performance operationRequired: ~8+ years of industrial experience in digital design ~ Strong knowledge of DDR or HBM memories ~ Proven experience designing or integrating memory controllers ~ Hands-on experience with AXI protocol ~ Proficiency in RTL design (Verilog or VHDL) ~ Experience with timing constraints and basic block-level testingDesired: Master’s degree or PhD Scripting skills (Python, Perl, Bash, TCL) Experience with version control (git, svn) Knowledge of coherency concepts and protocols Experience defining memory maps

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    hace 1 semana

    Madrid, España Beagle A tiempo completo

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