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Verification Engineer
hace 3 meses
- Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL?
- Want to join a very exciting Spain based semiconductor company?
If you can say to this, then please keep reading.
We're partnered with a genuinely exciting Barcelona based semiconductor organization and they're seeking a number of Verification Engineers to join them on a permanent basis, working fully onsite.
This company has some very aggressive growth plans and need to hire at least 20 engineers over the next 18 months.
Visa sponsorship is available if needed, not to mention free Spanish lessons to help you assimilate in Spain. International applicants are encouraged
Required skills:
- MSc or PhD in a related field
- Proficiency in SystemVerilog and UVM
- Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
- Experience with simulation and simulation tools
- Knowledge of revision control methodology and tools (git, svn)
- Experience in block level and subsystem or top level verification
- Experience with formal and dynamic verification
- Strong problemsolving skills and attention to detail
- Excellent communication and teamwork abilities
Sound good?
In return you'll receive an excellent yearly salary, flexible work schedules, and very good career progression, whilst working within a team of extremely talented individuals.