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Senior Dft Engineer

hace 4 meses

Barcelona, Barcelona, España Akuaro Work SLU A tiempo completo
In 2023, Brussels approved 8.1 billion euros to boost the development of semiconductor technologies in Europe.

The industry requires public aid to mobilize private investment, and in this chapter, it is expected to create 8,700 direct job opportunities.

With this, microchips may become the backbone of Europe's industrial competitiveness in the coming years.


Our partner, a direct collaborator in the RISC-V architecture, is actively involved in a fierce battle against the "monopoly" ARM, leading companies like Google to consider shifting their future processors towards this architecture.

This move addresses the growing need to incorporate AI into chips for mobiles, tablets, smartwatches, and ultimately any IoT device in the future.

They are currently seeking to add talented individuals like you to their team.


Today, they boast highly specialized professionals in this field and have forged alliances with key industry partners, in addition to running their own training academy to nurture critical talent for their business.

They are currently looking to onboard Senior Talent and Leads, and they invite you to be part of this exciting journey as a

DFT engineer, you will collaborate in designing and developing solutions for our

semiconductor portfolio. You will collaborate with the Package Team and the Backend Team to create

complex DFT solutions that need to deal with high frequency signals, performance requirements and

customer expectations.

Requirements:

  • Experience with DFT techniques applied in multiprocessor SoCs using DVFS methods
  • Experience with at least one of the leading EDA tools for DFT (Tessent, TestMax, Modus)
  • Experience with high frequency designs
  • Understanding of SoC RTL designs written in SystemVerilog, Verilog or VHDL
  • Experience with JTAG applied in multiprocessor SoC environment
  • Experience with MBIST, LBIST, IOBIST and at speed test methods
  • Proficiency of the test pattern generation and validation for highest fault coverage requirement
  • Experience with Scan chain
  • Knowledge of scan compression
  • Experience with Timing and Timings Constraints
  • Experience with basic block level testing
  • Strong problemsolving skills and attention to detail
  • Excellent communication and teamwork abilities
  • English level C 7 years of experience in the role
  • Bachelor, Master or PhD